This invention relates to a semiconductor device having a bipolar transistor and a method of manufacturing the same, and in particular, to a BiCMOS semiconductor device and a method of manufacturing the same.
Generally, a semiconductor device often includes a BiCMOS integrated circuit in which a bipolar transistor and a complimentary MOS (CMOS) transistor are formed on the same chip. Herein, the CMOS transistor is advantageous in structuring a logic circuit while the bipolar transistor is advantageous in constituting a linear circuit such as an amplifier circuit. The above BiCMOS integrated circuit has both advantages of the CMOS transistor and the bipolar transistor.
Such a BiCMOS integrated circuit often constitutes a SRAM which has a memory cell portion and a sense amplifier portion which is arranged at the periphery of the memory cell portion. In this event, the memory cell portion is composed of the CMOS transistors while the sense amplifier portion is composed of the bipolar transistors. Herein, it is to be noted that the SRAM consisting of the BiCMOS will be thereinafter referred to as a BiCMOS SRAM.
In such a BiCMOS SRAM, a MOS transistor region and a bipolar transistor region are placed adjacent to each other via a field oxide film. In this event, the MOS transistor has a drain region, a source region and a gate region while the bipolar transistor has a base region, an emitter region and a collector region. Further, an emitter electrode is formed on the emitter region.
In this case, the MOS transistor is covered with a first insulating layer in the MOS transistor region while the bipolar transistor is covered with a second insulating layer in the bipolar transistor region. Further, a first wiring layer is formed on the first insulating layer while a second wiring layer is formed on the second insulating layer.
Herein, the thickness of the second insulating layer in the bipolar transistor region becomes thinner than that of the first insulating layer in the MOS transistor region. This thickness difference is caused by the manufacturing process. Consequently, the height between the bipolar transistor and the second wiring pattern is generally different from the height between the MOS transistor and the first wiring pattern.
Under the circumstances, a first contact hole is formed in the first insulating layer in the MOS transistor region by the use of the known dry-etching process. At the same time, second contact hole is formed in the second insulating layer in the bipolar transistor region in the same manner. Further, a first contact plug is embedded in the first contact hole while a second contact plug is embedded in the second contact hole.
In this event, the second insulating layer in the bipolar transistor region is quickly etched as compared to the first insulating layer in the MOS transistor region. Consequently, the emitter electrode is excessively or partially etched. Thus, when the emitter electrode is excessively etched, the characteristic of the bipolar transistor is degraded.
Specifically, when the emitter electrode is partially etched, the thickness of the emitter electrode becomes thin. Consequently, the ratio of holes which recombine in the emitter electrode is reduced. As a result, the base current of the base region is increased. The increase of the base current reduces the direct current amplification factor of the bipolar transistor.
It is therefore an object of this invention to provide a semiconductor device which is capable of preventing reduction of a direct current amplification factor in a semiconductor device having a bipolar transistor.
It is another object of this invention to provide a BiCMOS semiconductor device which is operable at a high speed.
It is still another object of this invention to provide a method of manufacturing a semiconductor device or a BiCMOS semiconductor device which is capable of forming contact plugs in insulating layers which have different thickness and which are formed in a bipolar transistor region and a MOS transistor region.
According to this invention, a semiconductor device includes a bipolar transistor having at least an emitter region. An emitter electrode is formed on the emitter region. Further, a wiring pattern is formed over the emitter region. With such a structure, a plurality of contact plugs are formed to electrically connect the emitter electrode with the wiring pattern. In this event, the contact plugs are partially embedded in the emitter electrode in order to preventing reduction of the current amplification factor of the bipolar transistor.
Further, the semiconductor device (BiCMOS) includes a CMOS transistor which has at least source and drain regions and a bipolar transistor which has at least an emitter electrode and which is arranged adjacent to the CMOS transistor. In this event, a first insulating layer is formed on the CMOS transistor. Further, a first wiring pattern is formed on the first insulating layer and over the CMOS transistor. A first contact plug is formed in the first insulating layer to electrically connect either one of the source and drain regions with the wiring pattern.
On the other hand, a second insulating layer is formed on the bipolar transistor. Further, a second wiring pattern is formed on the second insulating layer and over the bipolar transistor. A plurality of second contact plugs are formed in the second insulating layer to electrically connect the emitter electrode with the second wiring pattern.
In this event, the second contact plugs are partially embedded in the emitter electrode in order to prevent the reduction of the current amplification factor of the bipolar transistor.
In the semiconductor device (BiCMOS), the current amplification factor of the bipolar transistor can be suitably determined in accordance with the purposes by selecting the number of the second contact plugs in accordance with the height difference between the first contact plug and the second contact plug.